1
SOLUTIONS MANUAL
DIGITAL DESIGN
WITH AN INTRODUCTION TO THE VERILOG HDL Fifth Edition
M. MORRIS MANO Professor Emeritus California State University, Los Angeles
MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs
rev 02/14/2012
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
2
CHAPTER 1 1.1
Base-10: Octal: Hex: Base-12
16 17 20 21 10 11 14 15
1.2
(a) 32,768
18 22 12 16
19 23 13 17
20 24 14 18
21 25 15 19
(b) 67,108,864 3
22 23 24 25 26 27 30 31 16 17 18 19 1A 1B 20 21
26 27 28 29 30 32 33 34 35 36 1A 1B 1C 1D 1E 22 23 24 25 26
31 37 1F 27
32 40 20 28
(c) 6,871,947,674
(4310)5 = 4 * 5 + 3 * 5 + 1 * 51 = 58010
1.3
2
(198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010 1.4
1.5
(435)8 = 4 * 82 + 3 * 81 + 5 * 80 = 28510
(345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 216 -1 = 65,53510 Hexadecimal equivalent: FFFF16 Let b = base (a) 14/2 = (b + 4)/2 = 5, so b = 6 (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8 (c) (2 *b + 4) + (b + 7) = 4b, so b = 11
1.6
(x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22 Therefore: 6 + 3 = b + 1m, so b = 8 Also, 6*3 = (18)10 = (22)8
1.7
64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8
1.8
(a) Results of repeated division by 2 (quotients are followed by remainders): 43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) Answer: 1111_10102 = FA16
3(0)
1(1)
(b) Results of repeated division by 16: 43110 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9
(a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DADA.B16 = 14*163 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
3
(e) 1010.11012 = 8 + 2 + .5 + .25 + .0625 = 10.8125
1.10
(a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310 (b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510
1.11
Reason: 110.0102 is the same as 1.100102 shifted to the left by two places.
1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 1110112 / 1012 = 5910 / 510 ≅ 1011.112 = 58.7510
1.12
(a) 10000 and 110111 1011 +101 10000 = 1610
1011 x101 1011 1011 110111 = 5510
(b) 62h and 958h 2Eh +34 h 62h
1.13
0010_1110 0011_0100 0110_0010 = 9810
2Eh x34h B 38 2 8A 9 5 8h = 239210
(a) Convert 27.315 to binary:
27/2 = 13/2 6/2 3/2 ½
Integer Quotient 13 6 3 1 0
Remainder + + + + +
½ ½ 0 ½ ½
Coefficient a0 = 1 a1 = 1 a2 = 0 a3 = 1 a4 = 1
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
4
2710 = 110112 .315 x 2 .630 x 2 .26 x 2 .52 x 2
= = = =
Integer 0 1 0 1
+ + + +
Fraction .630 .26 .52 .04
Coefficient a-1 = 0 a-2 = 1 a-3 = 0 a-4 = 1
.31510 ≅ .01012 = .25 + .0625 = .3125 27.315 ≅ 11011.01012 (b) 2/3 ≅ .6666666667 .6666_6666_67 x 2 .3333333334 x 2 .6666666668 x 2 .3333333336 x 2 .6666666672 x 2 .3333333344 x 2 .6666666688 x 2 .3333333376 x 2
Integer = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0
+ + + + + + + +
Fraction .3333_3333_34 .6666666668 .3333333336 .6666666672 .3333333344 .6666666688 .3333333376 .6666666752
Coefficient a-1 = 1 a-2 = 0 a-3 = 1 a-4 = 0 a-5 = 1 a-6 = 0 a-7 = 1 a-8 = 0
.666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110 .101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)). 1.14
` 1.15
(a)
0001_0000 1s comp: 1110_1111 2s comp: 1111_0000
(b)
0000_0000 1s comp: 1111_1111 2s comp: 0000_0000
(c)
1101_1010 1s comp: 0010_0101 2s comp: 0010_0110
(d)
1010_1010 1s comp: 0101_0101 2s comp: 0101_0110
(e)
1000_0101 1s comp: 0111_1010 2s comp: 0111_1011
(f)
1111_1111 1s comp: 0000_0000 2s comp: 0000_0001
(a)
25,478,036 9s comp: 74,521,963 10s comp: 74,521,964
(b)
63,325,600 9s comp: 36,674,399 10s comp: 36,674,400
(c)
25,000,000 9s comp: 74,999,999 10s comp: 75,000,000
(d)
00000000 9s comp: 99999999 10s comp: 100000000
1.16 15s comp: 16s comp: 1.17
C3DF 3C20 3C21
C3DF: 1100_0011_1101_1111 1s comp: 0011_1100_0010_0000 2s comp: 0011_1100_0010_0001 = 3C21
(a) 2,579 → 02,579 →97,420 (9s comp) → 97,421 (10s comp) 4637 – 2,579 = 2,579 + 97,421 = 205810 (b) 1800 → 01800 → 98199 (9s comp) → 98200 (10 comp) 125 – 1800 = 00125 + 98200 = 98325 (negative) Magnitude: 1675 Result: 125 – 1800 = 1675
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
5
(c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.18
1.19
Note: Consider sign extension with 2s complement arithmetic. (a)
0_10010 (b) 0_100110 1s comp: 1_01101 1s comp: 1_011001 with sign extension 2s comp: 1_01110 2s comp: 1_011010 0_10011 0_100010 Diff: 0_00001 (Positive) 1_111100 sign bit indicates that the result is negative Check:19-18 = +1 0_000011 1s complement 0_000100 2s complement 000100 magnitude Result: -4 Check: 34 -38 = -4
(c)
0_110101 (d) 1s comp: 1_001010 1s comp: 2s comp: 1_001011 2s comp: 0_001001 Diff: 1_010100 (negative) 0_101011 (1s comp) 0_101100 (2s complement) 101100 (magnitude) -4410 (result)
0_010101 1_101010 with sign extension 1_101011 0_101000 0_010011 sign bit indicates that the result is positive Result: 1910 Check: 40 – 21 = 1910
+9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913
1.20
+49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001→ 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a) (+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
6
(c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 7810 Result: (-29) + (-49) = -7810 1.21
+9742 → 009742 → 990257 (9's comp) → 990258 (10s) comp +641 → 000641 → 999358 (9's comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b) (+9742) + (-641) →009742 + 999359 = 009102 Result: (+9742) + (-641) = 9102 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -10383
1.22
6,514 BCD: ASCII: ASCII:
0110_0101_0001_0100 0_011_0110_0_011_0101_1_011_0001_1_011_0100 0011_0110_0011_0101_1011_0001_1011_0100
1.23 0111 0110 1101 0110 0001 0011 0001 0001 0001 0100 1.24
0001 ( 791) 1000 (+658) 1001
0100
1001 (1,449)
(a)
6 0 0 0 0 0 0 1 1 1 1 1.25
1001 0101 1110 0110 0100
3 0 0 0 1 1 1 0 0 0 1
(b)
1 0 0 1 0 1 1 0 1 1 0
1 0 1 0 0 0 1 0 0 1 0
Decimal 0 1 2 3 4 (or 0101) 5 6 7 (or 1001) 8 9
6 0 0 0 0 0 0 1 1 1 1
4 0 0 0 0 1 1 0 0 0 0
2 0 0 1 1 0 0 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1
Decimal 0 1 2 3 4 5 6 (or 0110) 7 8 9
(a) 6,24810 (b)
BCD: 0110_0010_0100_1000 Excess-3: 1001_0101_0111_1011
(c) (d)
2421: 6311:
0110_0010_0100_1110 1000_0010_0110_1011
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
1.26
7
6,248 9s Comp: 2421 code: 1s comp c: 6,2482421 1s comp c
3,751 0011_0111_0101_0001 1001_1101_1011_0001 (2421 code alternative #1) 0110_0010_0100_1110 (2421 code alternative #2) 1001_1101_1011_0001 Match
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
8 For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the 'number' of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.)
1.27
1.28
G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_11100101
1.29
Steve Jobs
1.30
73 F4 E5 76 E5 4A EF 62 73 73: F4: E5: 76: E5: 4A: EF: 62: 73:
0_111_0011 1_111_0100 1_110_0101 0_111_0110 1_110_0101 0_100_1010 1_110_1111 0_110_0010 0_111_0011
s t e v e j o b s
1.31
62 + 32 = 94 printing characters
1.32
bit 6 from the right
1.33
(a) 897
1.34
ASCII for decimal digits with even parity:
1.35
(b) 564
(0): 00110000 (4): 10110100 (8): 10111000
(1): (5): (9):
(c) 871
10110001 00110101 00111001
(d) 2,199
(2): (6):
10110010 00110110
(3): (7):
00110011 10110111
(a) a b c a f
b c
g
f g
1.36 a
b a f
g
b
f g
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
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CHAPTER 2 2.1
(a)
xyz
x+y+z
000 001 010 011 100 101 110 111
0 1 1 1 1 1 1 1
(x + y + z)' x' 1 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0
y'
z'
x' y' z'
xyz
(xyz)
(xyz)'
x'
y'
z'
x' + y' + z'
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
1 0 0 0 0 0 0 0
000 001 010 011 100 101 110 111
0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 0
1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
1 1 1 1 1 1 1 0
(b)
(c) xyz
x + yz
(x + y)
(x + z)
(x + y)(x + z)
xyz
x(y + z)
xy
xz
xy + xz
000 001 010 011 100 101 110 111
0 0 0 1 1 1 1 1
0 0 1 1 1 1 1 1
0 1 0 1 1 1 1 1
0 0 0 1 1 1 1 1
000 001 010 011 100 101 110 111
0 0 0 0 0 1 1 1
0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 1
0 0 0 0 0 1 1 1
(c)
(d) xyz
x
y+z
x + (y + z)
(x + y)
(x + y) + z
xyz
yz
x(yz)
xy
000 001 010 011 100 101 110 111
0 0 0 0 1 1 1 1
0 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1
000 001 010 011 100 101 110 111
0 0 0 1 0 0 0 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 1
2.2
(xy)z 0 0 0 0 0 0 0 1
(a) xy + xy' = x(y + y') = x (b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x (c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y (d) (A + B)'(A' + B')' = (A'B')(A B) = (A'B')(BA) = A'(B'B)A = 0 (e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c' (f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b
2.3
(a) ABC + A'B + ABC' = AB + A'B = B
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
10
(b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y) (c) (x + y)'(x' + y') = x'y'(x' + y') = x'y' (d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y) (e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0 (f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c') = c' + b'c' + a'b' = c' + a'b' 2.4
(a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) (x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz =[ (x + y)z' + z] + xy + wz = = (z + z')(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z
(c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5
(a) x
y
Fsimplified
F
(b) x
y Fsimplified
F
(c)
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
11
x
y
z Fsimplified
F
(d) A
B
0 Fsimplified
F
(e) x
y
z Fsimplified
F
(f)
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
12
x
y
z
F
Fsimplified
2.6
(a) A
B
C
F
Fsimplified
(b) x
y
z
F
Fsimplified
(c) x
y
F
Fsimplified
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
13
(d) w
x
y
z
F
Fsimplified
(e) A
B
C
D Fsimplified = 0
F
(f) w
x
y
z
F
Fsimplified
2.7
(a) A
B
C
D
F
Fsimplified
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
14
(b) w
x
y
z
F
Fsimplified
(c) A
B
C
D
F
Fsimplified
(d) A
B
C
D
F
Fsimplified
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
15
(e) A
B
C
D
F
Fsimplified
2.8
F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z') FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0 F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz
2.9
(a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x'y' (b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')' =a'c' + a'b + ab'c (c) F' = [z + z'(v'w + xy)]' = z'[z'(v'w + xy)]' = z'[z'v'w + xyz']' = z'[(z'v'w)'(xyz')'] = z'[(z + v + w') +( x' + y' + z)] = z'z + z'v + z'w' + z'x' + z'y' +z' z = z'(v + w' + x' + y')
2.10 2.11
(a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i) (b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j (a) F(x, y, z) = Σ(1, 4, 5, 6, 7) (b) F(a, b, c) = Σ(0, 2, 3, 7)
F = xy + xy' + y'z
2.12
F = bc + a'c'
xyz
F
abc
F
000 001 010 011 100 101 110 111
0 1 0 0 1 1 1 1
000 001 010 011 100 101 110 111
1 0 1 1 0 0 0 1
A = 1011_0001 B = 1010_1100
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
16
(a) (b) (c) (d) (e) 2.13
A AND B = 1010_0000 A OR B = 1011_1101 A XOR B = 0001_1101 NOT A = 0100_1110 NOT B = 0101_0011
(a) u
x
y
z
(u + x') Y = [(u + x')(y' + z)] (y' + z)
(b) u x y
x Y = (u xor y)' + x (u xor y)'
(c) u
x
y z
(u'+ x') Y = (u'+ x')(y + z') (y + z')
(d) u x y
z
u(x xor z) Y = u(x xor z) + y'
y' (e) u x y z
u yz
Y = u + yz +uxy
uxy
(f)
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
17
u x
y
Y = u + x + x'(u + y') x'(u + y') (u + y')
2.14
(a) x
y
z
F =xy + x'y' + y'z
(b) x
y
z
F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' (c) x
y
z
F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' (d) x
y
z
F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']'
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
18
(e) x
y
z
F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' 2.15
(a) T1 = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C') (b) T2 =T1' = A'BC + AB'C' + AB'C + ABC' + ABC = BC(A' + A) + AB'(C' + C) + AB(C' + C) = BC + AB' + AB = BC + A(B' + B) = A + BC
∑ (3, 5, 6, 7) = Π (0,1, 2, 4) T1 = A'B'C' + A'B'C + A'BC' A'B'
A'C'
T2 = A'BC + AB'C' + AB'C + ABC' + ABC AC'
AC
T1 = A'B' A'C' = A'(B' + C') BC T2 =AC' + BC + AC = A+ BC 2.16
(a) F(A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC = A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC) = (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC = B'(C' + C) + B(C' + C) = B' + B = 1 (b) F(x1, x2, x3, ..., xn) = Σmi has 2n/2 minterms with x1 and 2n/2 minterms with x'1, which can be factored and removed as in (a). The remaining 2n-1 product terms will have 2n-1/2 minterms with x2 and 2n-1/2 minterms with x'2, which and be factored to remove x2 and x'2. continue this process until the last term is left and xn + x'n = 1. Alternatively, by induction, F can be written as F = xnG + x'nG with G = 1. So F = (xn + x'n)G = 1.
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
19
2.17
(a) F = (b + cd)(c + bd) bc + bd + cd + bcd = Σ(3, 5, 6, 7, 11, 14, 15) F' = Σ(0, 1, 2, 4, 8, 9, 10, 12, 13) F = Π(0, 1, 2, 4, 8, 9, 10, 12, 13) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
F 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1
(b) (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd' = Σ (3, 4, 7, 11, 12,14, 15) = Π (0, 1, 2, 5, 6, 8, 9, 10, 13) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
F 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1
(c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd) = Σ (0, 1, 4, 5, 7, 8, 12, 13, 15) F = Π (2, 3, 6, 9, 10, 11, 14)
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
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(d) bd' + acd' + ab'c + a'c' = Σ (0, 1, 4, 5, 10, 11, 14) F' = Σ (2, 3, 6, 7, 8, 9, 12, 13, 15) F = Π (02, 3, 6, 7, 8, 12, 13, 15) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
F 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
21
2.18 (a)
(b)
wx y z
F
00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1
0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1
x y' z x' y' z w' x y w x' y w x y
F = xy'z + x'y'z + w'xy + wx'y + wxy F = Σ(1, 5, 6, 7, 9, 10 11, 13, 14, 15 )
5 - Three-input AND gates 2 - Three-input OR gates Alternative: 1 - Five-input OR gate 4 - Inverters
F
(c)
F = xy'z + x'y'z + w'xy + wx'y + wxy = y'z + xy + wy = yʹ′z + y(w + x)
(d)
F = y'z + yw + yx) = Σ(1, 5, 9, 13 , 10, 11, 13, 15, 6, 7, 14, 15) = Σ(1, 5, 6, 7, 9, 10, 11, 13, 14, 15)
(e) y' z x w
y
F
1 – Inverter, 2 – Two-input AND gates, 2 – Two-input OR gates
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
22
2.19
F = B'D + A'D + BD
2.20
ABCD
ABCD
ABCD
-B'-D 0001 = 1 0011 = 3 1001 = 9 1011 = 11
A'--D 0001 = 1 0011 = 3 0101 = 5 0111 = 7
-B-D 0101 = 5 0111 = 7 1101 = 13 1111 = 15
F = Σ(1, 3, 5, 7, 9, 11,13, 15) = Π(0, 2, 4, 6, 8, 10, 12, 14)
(a) F(A, B, C, D) = Σ(2, 4, 7, 10, 12, 14) F'(A, B, C, D) = Σ(0, 1, 3, 5, 6, 8, 9, 11, 13, 15) (b) F(x, y, z) = Π(3, 5, 7) F' = Σ(3, 5, 7)
2.21 2.22
(a) F(x, y, z) = Σ(1, 3, 5) = Π(0, 2, 4, 6, 7) (b) F(A, B, C, D) = Π(3, 5, 8, 11) = Σ(0, 1, 2, 4, 6, 7, 9, 10, 12, 13, 14, 15) (a) (u + xw)(x + u'v) = ux + uu'v + xxw + xwu'v = ux + xw + xwu'v = ux + xw = x(u + w) = ux + xw (SOP form) = x(u + w) (POS form) (b) x' + x(x + y')(y + z') = x' + x(xy + xz' + y'y + y'z') = x' + xy + xz' + xy'z' = x' + xy +xz' (SOP form) = (x' + y + z') (POS form)
2.23
(a) B'C +AB + ACD A
B
C
D
F
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
23
(b) (A + B)(C + D)(A' + B + D) A
B
C
D
F
(c) (AB + A'B')(CD' + C'D) A
B
C
D
F
(d) A + CD + (A + D')(C' + D) A
B
C
D
F
2.24
x ⊕ y = x'y + xy'
and (x ⊕ y)' = (x + y')(x' + y)
Dual of x'y + xy' = (x' + y)(x + y') = (x ⊕ y)' 2.25
(a) x| y = xy' ≠ y | x = x'y (x | y) | z = xy'z' ≠ x | (y | z) = x(yz')' = xy' + xz
Not commutative Not associative
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
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(b) (x ⊕ y) = xy' + x'y = y ⊕ x = yx' + y'x
Commutative
(x ⊕ y) ⊕ z = ∑(1, 2, 4, 7) = x ⊕ (y ⊕ z)
Associative
2.26 NAND (Positive logic)
Gate xy
z
xy
z
xy
z
LL LH HL HH
H H H L
00 01 10 11
1 1 1 0
11 10 01 00
0 0 0 1
NOR (Positive logic)
Gate
2.27
NOR (Negative logic)
NAND (Negative logic)
xy
z
xy
z
xy
z
LL LH HL HH
H L L L
00 01 10 11
1 0 0 0
11 10 01 00
0 1 1 1
f1 = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c' f2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c' a' b' a' a' b c' a' b c a' b c a b c a' b' c a' b c a b' c
a' c' b
f1
f2
c a' b c' a b' c'
a' b' b
f1
f2
c a b' c'
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
2.28
25
(a) y = a(bcd)'e = a(b' + c' + d')e
y = a(b' + c' + d')e = ab’e + ac’e + ad’e = Σ( 17, 19, 21, 23, 25, 27, 29) a bcde
y
a bcde
y
0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111
0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0
0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111
1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111
(b) y1 = a ⊕ (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef
y1 = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef a'-c--001000 = 8 001001 = 9 001010 = 10 001011 = 11
a'--d-000100 = 8 000101 = 9 000110 = 10 000111 = 11
a'---e000010 = 2 000011 = 3 000110 = 6 000111 = 7
001100 = 12 001101 = 13 001110 = 14 001111 = 15
001100 = 12 001101 = 13 001110 = 14 001111 = 15
001010 = 10 001011 = 11 001110 = 14 001111 = 15
011000 = 24 011001 = 25 011010 = 26 011011 = 27
010100 = 20 010101 = 21 010110 = 22 010111 = 23
010010 = 18 010011 = 19 010110 = 22 010111 = 23
011100 = 28 011101 = 29 011110 = 30 011111 = 31
011100 = 28 011101 = 29 011110 = 30 011111 = 31
011010 = 26 011001 = 27 011110 = 30 011111 = 31
a-c'd'e'100000 = 32 100001 = 33 110000 = 34 110001 = 35
-b' c--f
-b' -d-f
-b' --ef
001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47
001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47
000011 = 3 000111 = 7 001011 = 11 001111 = 15 100011 = 35 100111 = 39 101011 = 51 101111 = 55
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.
26
y1 = Σ (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ) y2 = Σ (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55) ab cdef
y1 y2
ab cdef
y1 y2
ab cdef
y1 y2
ab cdef
y1 y2
00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111
0 0 1 1 0 0 1 1
0 0 0 1 0 0 0 1
01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111
0 0 1 1 0 0 1 1
0 0 0 0 0 0 0 0
10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111
1 1 1 1 0 0 0 0
0 0 0 1 0 0 0 1
11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 11 0110 11 0111
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111
1 1 1 1 1 1 1 1
0 1 0 0 0 1 0 1
01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111
0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1
11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.